Soft-errors may occur in electronic circuitry as a result of quantum-type events. Soft-errors generally occur due to sub-atomic particles entering a silicon based integrated circuit (IC) and causing a disturbance in the distribution of charge (typically electrons) in the circuit. These disturbances may be a result of an intrinsically charged particle (e.g., an alpha particle resulting from radioactive decay occurring in impurities of packing materials) entering the IC. Other causes of soft errors include energetic neutrons (e.g., from cosmic rays or thermal neutrons) that undergo neutron capture (collision) with a nucleus of an atom in an IC, such as a silicon atom of the IC's substrate, or a dopant atom (such as boron) that is used to create transistors for the circuit in the substrate. Other sources of soft errors exist as well, such as energetic cosmic protons, for example.
Changes in charge distribution that result from such events can cause one or mores signal in an IC to unintentionally change from a digital 1 to a digital 0, or vice versa. Such changes in a signal may be termed “soft-errors” as the errors are generally transient and the affected IC will continue to operate normally after the effects of the “soft-error event” have dissipated, such as by resetting the disrupted signal to its original value, for example.
Memories implemented in integrated circuits (e.g., static random access memories, ternary content addressable memories, etc.) are particularly susceptible to soft-errors due to the density of such circuits as well as the relatively small dimensions of transistors used in such circuits as compared with the density and device sizes of transistors used in dynamic circuitry. For instance, transistors used in dynamic circuitry are typically much larger than transistors used in memories and less densely arranged, and therefore, are less susceptible to soft-errors as the amount of charge needed to change such signals may be orders of magnitude higher than the amount of charge required to change signals in memory circuits (such as in a single memory cell).
Parity and error code correction codes (ECC) are two techniques that may be used to protect memories from the effects of soft-errors. Parity is determined by counting the number of bits in a memory entry that are set to logic 1. For even parity, the parity bit is set to a logic 1 or logic 0 so that the total number of ones in the memory entry plus the parity bit is an even number. For odd parity, the parity bit is set to a logic 1 or logic 0 so that the total number of ones in the memory entry plus the parity bit is an odd number. If a soft-error occurs in a bit of such a memory entry, the parity bit will be incorrect and the error may be reported to software and/or hardware for appropriate error handling. Parity bits are stored in a memory along with the data that they are associated with.
Error correction codes are a set of encoded bits that are generated by encoding data stored in a particular memory location. The data for each entry of a memory structure may be encoded using an array of logic gates, for example. The error correction codes can then be used, on subsequent accesses to the data, to determine if a soft-error has occurred. The error correction codes can also be used to reconstruct the original data and repair the soft-error. As with parity bits, ECC bits are stored in a memory along with the data that they are associated with.
While parity and ECC are an effective way to detect, and/or detect and correct soft-errors in random access memories, implementing such approaches in certain memory structures may be complex and expensive. For instance, implementing parity or ECC in a ternary content addressable memory (TCAM), so that parity and ECC operations are done during compare operations (memory accesses) would require a parity or ECC protection circuit per TCAM entry. Such an approach would be extremely complex to design and would result in significant increases in the size of such memories on a silicon chip, thus significantly increasing the design complexity, development costs and manufacturing costs of such devices.